|
P32A 001000 |
rt |
rs |
sa |
SHRA.QB 0 |
000 |
111 |
111 |
111 |
|
P32A 001000 |
rt |
rs |
sa |
SHRA_R.QB 1 |
000 |
111 |
111 |
111 |
|
6 |
5 |
5 |
3 |
1 |
3 |
3 |
3 |
3 |
SHRA[_R].QB |
Shift Right Arithmetic Vector of Four Bytes | |
SHRA.QB rt, rs, sa |
DSP-R2 |
Shift Right Arithmetic Vector of Four Bytes |
SHRA_R.QB rt, rs, sa |
DSP-R2 |
Shift Right Arithmetic Vector of Four Bytes |
Shift Right Arithmetic Vector of Four Bytes
To execute an arithmetic right shift on four independent bytes by a fixed number of bits.
rt = round(rs31..24 >> sa) || round(rs23..16 >> sa) || round(rs15..8 >> sa) || round(rs7..0 >> sa)
The four byte elements in register rs are each shifted right arithmetically by sa bits, then written to the corresponding vector elements in destination register rt. The sa argument is interpreted as an unsigned three-bit integer taking values from zero to seven.
In the rounding variant of the instruction, a value of 1 is added at the most significant discarded bit position of each result prior to writing the rounded result to the destination register.
No data-dependent exceptions are possible.
The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.
SHRA.QB
ValidateAccessToDSP2Resources()
tempD7..0 = ( GPR[rs]31)sa || GPR[rs]31..24+sa )
tempC7..0 = ( GPR[rs]23)sa || GPR[rs]23..16+sa )
tempB7..0 = ( GPR[rs]15)sa || GPR[rs]15..8+sa )
tempA7..0 = ( GPR[rs]7)sa || GPR[rs]7..sa )
GPR[rt]31..0 = tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
SHRA_R.QB
ValidateAccessToDSP2Resources()
if ( sa2..0 = 0 ) then
tempD7..0 = GPR[rs]31..24
tempC7..0 = GPR[rs]23..16
tempB7..0 = GPR[rs]15..8
tempA7..0 = GPR[rs]7..0
else
tempD8..0 = ( GPR[rs]31)sa || GPR[rs]31..24+sa-1 ) + 1
tempC8..0 = ( GPR[rs]23)sa || GPR[rs]23..16+sa-1 ) + 1
tempB8..0 = ( GPR[rs]15)sa || GPR[rs]15..8+sa-1 ) + 1
tempA8..0 = ( GPR[rs]7)sa || GPR[rs]7..sa-1 ) + 1
endif
endif
Reserved Instruction, DSP Disabled